In large high energy physics experiments, detectors may have more than 107 electronic channels. For production of such enormous quantities of electronic circuits, monolithic techniques are essential. However, replacing the discrete and hybrid circuits of the past with monolithic integrated versions poses many design challenges. The constraints of low noise, high precision, and high speed remain severe while we strive to implement circuits that are highly integrated, consume lower power, and are manufacturable at low cost. At Instrumentation Division, researchers use CMOS technology to make integrated front-end circuits for various types of radiation sensors.

The classes of circuits include:

  • Low noise charge-sensitive preamplifiers.
  • Pulse shaping active filters.
  • Precision, on chip calibration circuits.
  • Timing discriminators.
  • Analog multiplexors.

PEAK DETECTOR ASIC for accurate and efficient processing of high-rate pulse signals from highly segmented detectors. In contrast to conventional approaches, this circuit affords a dramatic reduction in data volume through the use of precision peak detectors and time-to-amplitude converters together with fast arbitration and sequencing logic to concentrate the data before digitization. In operation the circuit functions like a data-driven analog first-in, first-out (FIFO) memory between the preamplifiers and the ADC. Peak amplitudes of pulses arriving at any one of the 32 inputs are sampled, stored, and queued for readout and digitization through a single output port. Analog memories absorb the Poisson fluctuations of the input pulse rate allowing digitization at a conversion rate comparable to the average input rate. Hit timing, pulse risetime, and channel address are available at the output. Examples of applications that can benefit from this approach include X-ray spectroscopy and position sensing with multi-element detectors.

Cathode Strip Chamber ASIC for the muon spectrometer in the ATLAS experiment at CERN. ASIC consists of 25 preamplifier and high-order complex Gaussian 70 nSec bipolar shaping amplifiers. Fabricated in 0.5µm Agilent Technolgies CMOS process, operates off a single 3.3V supply and dissipates 35 mW/channel and the die size is 3.3mm x 5.8mm. The device is packaged in a 100-pin PQFP molded package and has been successfully integarated on to the CSC chambers on the Amplifier Shaper Memory (ASM) boards.

Peak Detector & Derandomizer (PDD) ASIC for Highly Efficient Energy and Timing Extraction in High-Rate Applications.

Last Modified: Wednesday, 06-Feb-2013 22:33:56 EST